Across all sectors, industries, and geographies, demands continue for the electronic industry to provide products that are lighter, faster, smaller, multi-functional, more reliable, and more cost-effective. In order to meet these requirements of so many and varied consumers, more electrical circuits need to be more highly integrated to provide the functions demanded. Across virtually all applications, there continues to be growing demand for reducing size, increasing performance, and improving features of integrated circuits.
The seemingly endless requirements are no more visible than with products in our daily lives. Smaller and denser integrated circuits are required in many portable electronic products, such as cellular phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
As the demand grows for smaller electronic products with more features, manufacturers are seeking ways to include more features as well as reduce the size of the integrated circuits. Increased miniaturization of electronic products typically involves miniaturization of components, greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost. As new generations of electronic products are released, the number of integrated circuits used to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these products increases.
Semiconductor package structures continue to advance toward miniaturization to increase the density of the components that are packaged therein while decreasing the sizes of the end products having the IC products. This is in response to continually increasing demands on information and communication apparatus for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.
Different challenges arise from increased functionality integration and miniaturization. For example, a semiconductor product having increased functionality may be made smaller but may still be required to provide a large number of inputs/outputs (I/O) interface. The size reduction increases the I/O density for the integrated circuit package and its respective integrated circuit carriers.
The ever-increasing I/O density trend presents a myriad of manufacturing problems. Some of these problems reside integrated circuit manufacturing realm. Others problems involve mounting these increase I/O density integrated circuits on carriers for packaging.
For example, attaching integrated circuits onto a carrier typically involve subjecting the carrier to elevated temperatures for forming electrical and mechanical connections between the integrated circuit and the carrier. These elevated temperatures may cause the integrated circuits and the carrier to expand at different rates creating problems at the contact points.
For example, flip-chip packaging technology has found widespread use because of its advantage in size, performance, flexibility, reliability and cost over other packaging methods. Flip chip packaging employs direct electrical connection of face-down integrated circuit (IC) chips onto substrates, circuit boards, or carriers, by means of conductive bumps on the chip bond pads, replacing older wire bonding technology where face-up chips sit on substrates with wire connection to each bond pad.
During flip chip packaging, the IC chip with bump array can be placed facedown on a substrate with a matching bump array, and the assembly is heated to make a solder connection. Typically, flip chip packages provide fine bump pitch, small bump pad diameter, and large die size. The flip chip attributes in conjunction with the heating or reflow process cause manufacturing problems. For example, the expansion rate difference between the integrated circuit and the substrate during reflow results in reliability problems at the connection between the integrated circuits and the substrate.
More specifically, concerns regarding environmental contamination are driving the electronics industry to implement lead-free solder alloys. This includes the material systems used to attach or connect integrated circuit within electronic products. For example, typical flip chip bonding techniques utilizes coined SOP (Solder On Pad) due to wetting capability and uniformity of height. However, in the case of conventional SOP, the failure caused by a crack in the SOP due to stress from the coefficient of thermal expansion (CTE) mismatch between underfill and substrates at intermetallic compound (IMC) layer.
Typical flip chip connections with coined SOP form IMC layers at the substrate side and at the flip chip side. Although the IMC layers are needed to ensure good solder joint, the thickness of the IMC layers may weaken the solder joint. IMC layers tend to be more brittle resulting in weaker solder joint connections and attachment of the flip chip with the substrate. The fragility of the solder joint may increase over time and elevated temperatures through the expansion of the IMC layer parallel to the substrate and the flip chip creating reliability problems.
Thus, a need still remains for an electronic system providing low cost manufacturing, improved yield, and improved reliability. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.